Equix Technologies ★ 3.0

• Negotiable salary according to ability
• 100% salary during probation period
• Salary review 2 times/year.
• 13th month salary bonus, performance bonus, Tet bonus, birthday bonus,...
• Bao Viet Insurance for official employees from 6 months.
• Social insurance, Health insurance, Unemployment insurance when becoming an official employee.
• Sick regime, filial piety, encouraging young talents,...
• Young, dynamic and enthusiastic environment.
• Flexible working time.
• Get 1-1 training with Manager or Senior.
• Annual vacation, many teambuilding activities.
• Support club activities such as Badminton, Yoga, Soccer, Swimming-Biking-Running,...

Key responsibilities

• Review, critique, and optimize algorithms, data architectures and data flows implemented on FPGA to meet latency and throughput targets.
• Propose FPGA platforms and architectures for one or more products (board selection, FPGA family, toolchain, possible HLS use).
• Design the overall FPGA system architecture; define requirements for internal and third‑party IP cores.
• Directly design, simulate, implement and optimize complex modules/algorithms (pipelining, parallelism, fixed‑point/DSP usage, time‑critical paths).
• Lead and provide technical direction for FPGA engineers: assign tasks, perform RTL/code reviews, and resolve technical bottlenecks.
• Establish and maintain FPGA design processes and standards (coding style, simulation and verification flows, timing closure, floorplanning, review checklists).
• Define and execute verification strategy: testbenches, simulation (ModelSim/Questa), hardware‑in‑the‑loop, regression testing and CI for FPGA deliverables.
• Optimize resource usage (LUTs, FFs, BRAM, DSP slices), manage constraints, and ensure timing closure using toolchains (Xilinx/Intel).
• Work closely with algorithm, system software, networking, firmware and operations teams to integrate solutions, measure latency and deploy into production environments.
• Participate in product troubleshooting, post‑deployment performance tuning and support operations as needed.

Job requirements Education and experience

• Bachelor’s degree or higher in Computer Science, Information Technology, Electronics/Telecommunications Engineering, Mathematics‑Computer Science, or related technical field.
• Minimum 3 years of hands‑on experience with FPGA development for real products.
• Experience in low‑latency domains is a strong advantage.

Technical skills

• Proficient in hardware description languages: Verilog/SystemVerilog; VHDL is a plus.
• Experience with toolchains: Xilinx Vivado/ISE/SDK, Intel Quartus, ModelSim/Questa; Vivado HLS if applicable.
• Deep understanding of digital logic design, pipelining, timing closure, floorplanning, clock domain crossing and reset strategies.
• Experience with high‑speed interfaces: PCIe, Ethernet (10/25/40/100GbE), DMA, MMIO, and TCP/UDP offload techniques.
• Proficiency in optimizing DSP usage, BRAM, resource management and latency‑sensitive designs.
• Verification experience: UVM, testbench development, simulation, hardware regression and integrating FPGA into real‑time systems.
• Scripting/programming skills: Python, Tcl, Bash; experience with Git; CI/CD for FPGA is a plus.
• Comfortable working on Linux; able to debug systems, analyze logs and profile latency.
• Knowledge of low‑latency networking, time synchronization (PTP), and kernel bypass technologies (DPDK, XDP) or RDMA is advantageous.
• Firmware & software integration: experience developing embedded firmware and low‑level software for FPGA/SoC platforms (bare‑metal, RTOS, or embedded Linux).
• C/C++ proficiency: experience developing performance‑sensitive C/C++ code, driver/user‑space interaction, and cross‑compilation toolchains.
• Device driver and boot/bring‑up experience: Linux kernel modules, U‑Boot, board bring‑up and debugging using JTAG, openOCD, or vendor tools.
• Hardware/architecture understanding: knowledge of SoC architectures (ARM Cortex‑A/R/M, HPS), AXI/AMBA interconnects, memory maps, cache coherency, and board‑level concerns (power, clocks, signal integrity).

Soft skills

• Strong analytical skills and ability to solve complex system‑level problems.
• Excellent teamwork and communication skills to collaborate with algorithm, software, firmware and ops teams.
• Experience mentoring and reviewing work of junior engineers.
• Proactive, able to work under pressure in a fast‑paced development environment.

Preferred / Nice‑to‑have

• Experience with board bring‑up, power and thermal considerations for FPGA products.
• Prior work experience in finance/fintech or other latency‑critical industries.
• Demonstrated firmware development experience (embedded C/C++, RTOS, bare‑metal, embedded Linux).
• Experience writing and maintaining device drivers, bootloader configuration and cross‑platform integration between FPGA fabric and CPU subsystems.
• Solid understanding of hardware architecture and PCB/board-level design implications (schematics, SI/PI basics).
• Open‑source contributions, publications, or personal FPGA/firmware projects demonstrating expertise.

Apply now via:

• Email: [email protected]
• Phone: 0867249182
• Recruitment Facebook page: EQUIX TECHNOLOGIES