CÔNG TY TNHH HCL VIỆT NAM. 4.0 ★

• Professional experience of executing physical design projects from 4 years of experience.
• Proven ability in technically leading a small/medium size team for executing projects preferred
• Hands on experience on the entire PD Flow from RTL to GDSII
• Should have good understanding of Floor planning, Power Planning, Placement & Optimization, CTS, Routing, Design Convergence and Sign-off with in depth expertise in at least one of these domains
• Working knowledge about OCV, MM/MC optimization and multi power designs (Level shifters, Isolation cells etc)
• Exposure to static timing analysis fixes including automated ECO generation
• Strong in areas on CTS and skew fixing
• Library preparation in any environment (Synopsys, Cadence etc)
• Working knowledge on Physical verifications tasks at lower nodes (data base merging/DRC/LVS/ERC/PERC/Antenna/ESD/LUP analysis/fixing ) at block level/chip level
• Job would require complete ownership from netlist/RTL to GDS for blocks at Block level OR full chip level
• Exposure to IP Hardening for blocks like SERDES, USB PHY, MIPI, SATA will be an added advantage
• Working knowledge of scripting language like Perl, TCL will be considered a plus
• Candidate needs to be self-driven and confident in reporting out status and sharing technical results with customers
• Must have the ability to present to senior management, work in a geographically dispersed team and be aware of cross-cultural nuances
• Should be able to define project milestones, identify risks and call out mitigation plans