Bán dẫn FPT - FPT Semiconductor

About the Role

FPT Semiconductor is looking for bright ASIC engineers with excellent analytical and technical skills to join our fast-paced SoC team. This is a great opportunity to lead the RTL Design, Full Flows, and Methodology for high-performance ASICs that enable AI acceleration and Ultra-HD video processing in our next-generation smart camera designs.

You will play a critical role in developing a "Full SoC" solution comparable to industry benchmarks , integrating complex subsystems for Image Signal Processing (ISP), Neural Processing Units (NPU), and Video Codecs.

Job Description

This role gives you ownership of all aspects of design and development for large-scale SoCs, SoC blocks, and sub-systems.

• SoC Top-Level & Sub-system Design:

+) Design and integrate the SoC top-level architecture, including CPU Subsystems (ARM Cortex-A series), AI Subsystems (NPU/NNIE engines), and Video/Image Subsystems (ISP, VI/VO pipelines).

+) Handle internal/external IP integration for critical high-speed interfaces, including MIPI CSI/DSI (Sensor inputs), DDR4/LPDDR4 Controller, USB 3.0, PCIe, and Gigabit Ethernet (GMAC).

+) Design and verify the AMBA Bus Interconnect (AXI/AHB/APB) to ensure high-bandwidth efficiency for 4K/8K video streams.

• Design Flow & Methodology:

+) Develop integration specs and perform RTL design for infrastructure components: Clocking, Reset distribution (POR/RTC), and System Control.

+) Develop and implement Low Power Design (UPF) strategies for complex multi-power island and voltage island designs, critical for thermal management in compact camera SoCs.

+) Run comprehensive Quality Checks (QC) including Linting, CDC (Clock Domain Crossing), RDC (Reset Domain Crossing), and Logical Equivalence Checks (LEC).

• Implementation & Collaboration:

+) Work closely with Chip Architecture, Design Verification, Physical Design, DFT, and FPGA teams to achieve SoC tape-out goals on schedule.

+) Support the synthesis flow, generate netlists, and assist in timing closure (STA) for high-frequency blocks (e.g., NPU @ 1GHz+, DDR @ 3200Mbps).

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• From 10 years of hands-on experience in ASIC/SoC digital design or complex FPGA development.
• Proven track record of working on Front-End (FE) design, including RTL design, synthesis, and QC flows for large-scale SoCs.
• Expert knowledge of Verilog/SystemVerilog for RTL coding.
• Strong domain knowledge in Camera/Multimedia SoCs (Highly Preferred):

+) Familiarity with ISP pipelines (3A, WDR, 3DNR, DIS) and Video Codecs (H.264/H.265 standards).

+ Experience integrating AI/NPU accelerators for Computer Vision tasks (Object detection, Face recognition).

• IP Integration Skills: Deep understanding of standard interfaces such as MIPI Rx/Tx, DDR3/4/LPDDR4, SDIO 3.0, I2C/SPI/UART, and GMAC.
• Low Power Mastery: Extensive experience developing power intent (UPF/CPF) for designs with aggressive power gating and dynamic voltage scaling.
• Backend Familiarity: Familiarity with DFT (Scan, BIST, JTAG) and Static Timing Analysis (STA) helps in cross-functional collaboration.

Benefit & Perks

Successful candidates will be part of a friendly, motivated and committed talent teams with various benefits and attractive offers:

• Competitive salary in labor market
• Project bonuses when you join ODC (Offshore Development Center) projects
• 100% full salary in probation period
• Work with cutting-edge technologies including AI on Chip, 4K/8K Video Processing, and advanced semiconductor process nodes.
• “FPT care” health insurance provided by PIJICO and is exclusive for FPT employees
• Recharge and relax with paid annual summer vacation
• Internal Training (Technical & Functional). Scope of English Training
• Working time: 9:00 AM-6:00 PM From Mondays to Fridays

Contact point

If you are interested in this position, please send your resume and cover letter to email: [email protected] (Ms. Thu Huong – Mobile phone: 036.390.4039).