Cadian Việt Nam

Opportunities

• SNPS is the world number one IP provider. Work with many experts from around the world and talented highly motivated Viet Nam engineering team.
• Have opportunity to have experience with the best set of tools in the industry to support for your design tasks.
• Professional, innovative, fair and fun working environment. Strong culture company.
• Competitive salary and benefit. Strong support from company for health: Insurance, Sport clubs: Football, Ping-Pong, Badminton, Yoga, Zumba …
• Strong support from company for team building, social activities: Team trip, Family Day…
• Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
• Chance to work with bleeding edge technologies like: 2.5D/3D IC, High-speed Die to Die interfaces that enable Data Center, AI/ML, 5G applications.
• Clear career path of self-development to either Technical Expert or Design Leader/Manager
• Travel to USA, Europe, and Asia for training or on-site support.
• Showcase your brilliant ideas in conferences that sponsored by Synopsys
• Contribute to the growth of Viet Nam semiconductor industry with many big programs of Synopsys for universities and design community.
  
  

Job Descriptions

Candidates do not have to have experience on all the tasks below, there will be trainings to new engineers to adapt with Synopsys design and flows.

• Work on custom layout Analog IPs like High Speed IOs, PLL, DLL, Bandgap, High Speed macros for PHY, Clock trees...
• Floor planning, power design, signal routing strategy, EMIR awareness, parasitic optimization for layout blocks from schematics
• Understand and apply Analog Layout techniques to ensure design meet performance with minimum area and good yield.
• Participate in building and enhancing layout flow for faster, higher quality design process.
• Do layout verification for DRC/LVS/ERC/ANT/ESD/DFM
• Do PERC verification for ESD/LUP checks
• Complete all design quality checks and data quality checks
• Work with Place and Route engineer to integrate analog layouts into top level.
• Work with Package team to ensure the integration of top die and package
• Do design reviews across global team
• May collaborate in package design (interposer design, RDL design)
• Work closely with design team in Viet Nam, USA, Canada and other countries to ensure the success of the whole product.
• May join research programs to implement new ideas for future products and flows
• May lead a layout team to complete a full design block
• Mentor junior layout engineers or interns
  
  

Skills Requirements

• BS in Electronics Engineering, Electromechanics, Physics, Telecommunications.
• 3-8 years of experience in custom layout.
• Familiar with Layout entry tools: Cadence, Synopsys
• Familiar with Layout verification tools: Mentor Calibre, Synopsys ICV
• Understand basic semiconductor fabrication processes
• Understand MOSFET fundamentals
• Understand layout techniques for high speed, matching, ESD, Latchup, Antenna, EMIR.
• Experienced with mentoring/leading junior layouts to complete a design.
• Experienced with writing layout review presentations and layout verification reports
• Good English communication
• Strong team player
• Self-motivated, humble, honest and willing to learn.
  
  

Synopsys delivers the most trusted and comprehensive silicon to systems design solutions, accelerating technology innovation. We partner closely with our customers to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Companies trust Synopsys to pioneer new technologies to help them get to market faster without compromise.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.