MARVELL VIETNAM LLC ★ 4.4

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

Built on decades of expertise and execution, Marvell’s custom Processor/ASIC solution offers a differentiated approach with a best-in-class portfolio of data infrastructure intellectual property (IP) and a wide array of flexible business models. In this unique role, you’ll have the opportunity to work on both the physical design and methodology for future designs of our next-generation, high-performance processor chips in a leading-edge CMOS process technology, targeted at server, 5G/6G, automotive, and networking applications.

What You Can Expect

• You will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.
• You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools.
• Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks.
• You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.
• Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level. This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.
  
  

What We're Looking For

To be successful in this role you must:

• Have completed a Bachelor’s Degree in Electrical/Computer Engineering, Computer Science, or related fields and have 1-3 years of related professional experience OR a Master’s degree and/or PhD in Electrical/Computer Engineering, Computer Science, or related fields. In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis.
• Good understanding of standard RTL to GDS flows and methodology
• Good scripting skills in languages such as Perl, tcl, and Python
• Good object-oriented programming skills
• Good understanding of digital logic and computer architecture
• Knowledge of Verilog/VHDL
• Good communication skills and self-discipline contributing in a team environment
  
  

Additional Compensation And Benefit Elements

• Competitive salary, plus 13th-month salary and performance-based bonus
• RSUs (Restricted Stock Units) for new joiners and on-going annually
• Premium health & accident insurance for you and your family (spouse and children)
• Annual medical check-up at a designated hospital arranged by Marvell
• Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays
• Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more.
  
  

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.