Synopsys Việt Nam ( Piktec - Time Partition Testing ) ★ 3.6

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a highly motivated individual with a passion for physical design and implementation of complex Mixed Signal IPs and test chips. With a strong background in physical design, you thrive on solving intricate problems and enjoy collaborating with cross-functional teams. You have a deep understanding of the full design cycle from RTL to GDSII and are adept at using Synopsys tools and methodologies. Your excellent communication skills enable you to convey complex ideas to various stakeholders, and your scripting skills in Perl, Tcl, and Python enhance your efficiency and problem-solving capabilities. You are autonomous, make timely decisions, and can handle interruptions while maintaining focus on your goals.

What You’ll Be Doing:

• Leading the physical implementation of high-speed interface IPs and test-chips from RTL to GDS, ensuring timing and physical sign-off.
• Collaborating closely with front-end, analog, CAD, and product teams to achieve project goals.
• Utilizing Synopsys tools such as Design Compiler, Fusion Compiler, Primetime, Primetime SI, ICC2, Star-RCXT for design execution.
• Developing and applying CAD automation methods to streamline design processes.
• Ensuring the physical design meets performance, power, and size requirements of target applications.
• Staying updated with the latest industry trends and incorporating best practices into your work.
  
  

The Impact You Will Have:

• Contributing to the successful tape-out of high-speed interface IPs and test-chips across multiple process technologies.
• Enhancing the efficiency and performance of Synopsys' physical design projects.
• Driving innovation in chip design and verification processes.
• Helping customers integrate more capabilities into their SoCs, meeting unique performance, power, and size requirements.
• Reducing risk and accelerating time-to-market for differentiated products.
• Collaborating with cross-functional teams to deliver high-quality design solutions.
  
  

What You’ll Need:

• BE or MSEE with 2+ years of physical design experience
• Intimate knowledge of the full design cycle from RTL to GDSII, including chip level.
• Solid engineering understanding of IC design, implementation flows, and methodologies for deep submicron design.
• Proficiency in using Synopsys tools such as Design Compiler, Fusion Compiler, Primetime, Primetime SI, ICC2, Star-RCXT, etc.
• Strong software and scripting skills in Perl, Tcl, and Python.
  
  

Who You Are:

• Excellent communicator with the ability to convey complex ideas to different levels of abstraction.
• Autonomous and capable of making timely decisions.
• Able to handle interruptions and maintain focus on goals.
• Collaborative team player who enjoys working with cross-functional teams.
• Innovative thinker who stays updated with industry trends and best practices.
  
  

The Team You’ll Be A Part Of:

You will be part of the Synopsys Mixed-Signal IP organization, a team dedicated to the physical implementation of complex Mixed Signal IPs and test chips. This team collaborates closely with multiple functional groups including front-end, analog, CAD, and product teams to deliver high-quality design solutions that meet the unique performance, power, and size requirements of our customers’ applications.

Rewards and Benefits:

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.