Synopsys Việt Nam ( Piktec - Time Partition Testing ) ★ 3.6

Introduction
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security.

*Position: ASIC Digital Intern
What You Will Learn:
- ASIC design flow, RTL design flow, and Design Verification flow
- RTL coding using Verilog, SystemVerilog
- Testbenches writing, RTL verification, Universal Verification Methodology (UVM)
- Design for Test (Synthesis, Static Timing Analysis, Scan insertion, ATPG)
- Presentation skills, teamwork, task management, etc...

*Position: Analog Design Intern
- Stage 1: Fundamental Training
Training for fundamental knowledge of IC design
- Stage 2: Lab-work
+ Intern will be mentored to work on Circuit Labwork and Layout Labwork
+ Lab-work will contains all the basic requirements of a real project so that interns will be very familiar with the real jobs, such as: task planning, weekly status reports, design gate review, and evaluation,...
+ At the end of the internship program, the intern will be evaluated for performance and advised for a suitable job in IC Design Career path.

Benefits & Opportunities:
- Monthly internship allowance
- Be trained for fundamental knowledge of IC design.
- Be trained for key soft skills as professional engineers.
- Join real IC design projects with Synopsys teams. Mentored by experienced Synopsys engineers.
- Opportunity to become official Synopsys employees.
- Experience a real working environment and enjoy team activities.
- Support thesis: be provided with interesting topics and guided by dedicated engineers.