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Cập nhật 09/11/2024 10:51
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Công ty Cổ phần LawSoft
Analog Design, Staff Engineer
LawSoft
22 việc làm 19 lượt xem
Thông tin cơ bản
Mức lương: Thỏa thuận
Chức vụ: Nhân viên
Ngày đăng tuyển: 28/10/2024
Hạn nộp hồ sơ: 27/11/2024
Hình thức: FULL_TIME
Kinh nghiệm: 5 - 6 năm
Số lượng: 1
Giới tính: Không yêu cầu
Nghề nghiệp
Ngành
Job Title: Analog Design, Staff Engineer

Opportunities

  • SNPS is the world number one IP provider. Work with many experts from around the world and talented highly motivated Viet Nam engineering team.
  • Have opportunity to have experience with the best set of tools in the industry to support for your design tasks.
  • Professional, innovative, fair and fun working environment. Strong culture company.
  • Competitive salary and benefit. Strong support from company for health: Insurance, Sport clubs: Football, Ping-Pong, Badminton, Yoga, Zumba …
  • Strong support from company for team building, social activities: Team trip, Family Day…
  • Opportunity to get in touch with the complete design flow of a real complicated Analog Mixed Signal Design from specification to silicon.
  • Chance to work with bleeding edge technologies like: 2.5D/3D IC, High-speed Die to Die interfaces that enable Data Center, AI/ML, 5G applications.
  • Clear career path of self-development to either Technical Expert or Design Leader/Manager
  • Travel to USA, Europe, and Asia for training or on-site support.
  • Showcase your brilliant ideas in conferences that sponsored by Synopsys
  • Contribute to the growth of Viet Nam semiconductor industry with many big programs of Synopsys for universities and design community.

Job Descriptions

Candidates do not have to have experience on all the tasks below, there will be trainings to new engineers to adapt with Synopsys design and flows.

  • Design circuit for Analog IPs like High Speed IOs, PLL, DLL, Bandgap, Clock trees, Calibration circuits... for Die to Die, UCIe, DDR, HBM, Serdes PHY of Synopsys.
  • Work closely with layout engineer to make sure layout quality. Perform post layout verifications.
  • Design analysis and solve problems of noise, margin, signal integrity, power integrity.
  • Complete all design quality checks and data quality checks
  • Do design reviews across global team
  • Work with digital/system engineer to integrate analog designs into mixed signal system. Perform mixed signal verification which combining both analog and digital blocks.
  • Design test chip architecture to test analog designs.
  • Build up test cases and run tests in the Synopsys Laboratory to prove design work in silicon.
  • May join research programs to implement new ideas for future products and flows.
  • May lead a team to develop a completed design.
  • Training for junior engineers and interns

Skills Requirements:

  • BS/MS/PhD in Electronics Engineering, Electromechanics, Telecommunications.
  • 5+ years of experience in Analog, Mixed Signal, Memory or Custom logic Circuit design.
  • Solid knowledge of CMOS Analog design knowledge and techniques
  • Solid skill with circuit design tools: SNSP Custom Designer or Cadence Virtuoso
  • Solid understanding circuit simulation tools: Hspice or Spectre or Custom Sim…
  • Solid understanding of layout effects on circuit performance.
  • Experienced with writing design review presentations and circuit verification reports
  • Is a plus: Have experience with High Speed PHY design, IO design, DLL/PLL designs.
  • Good English communication both verbally and in writing
  • Great team player, willing to support others.
  • Highly responsible, result oriented.
  • Self-motivated and highly enthusiasm in technology and solving problems
  • Leadership skill and experience is a plus

Synopsys delivers the most trusted and comprehensive silicon to systems design solutions, accelerating technology innovation. We partner closely with our customers to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. Companies trust Synopsys to pioneer new technologies to help them get to market faster without compromise.
Khu vực
Báo cáo

Quy mô:
200 - 500 nhân viên
Địa điểm:
17 Nguyễn Gia Thiều, P.6, Q.3, TP.HCM

Công Ty TNHH Thư Viện Pháp Luật

Số 17 Nguyễn Gia Thiều, P6, Q3, TP. HCM 

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