Description

The Role

In this role, you will be responsible for ASIC implementation, including synthesis, floor-planning, place and route, timing closure, on our cutting edge ARMv8 based server on chip solutions (X-Gene) that will be the backbone of future data centers and also the AI Inference Server. You will be interacting on a daily basis with our design team worldwide and will work on the latest technology (3nm and 5nm) nodes available in the industry.

What The Team Wants You To Know

Ampere is looking for motivated team players who are ready to work in a startup like culture. Our mantra is “Ampere First!” and as part of the Ampere team, we are looking for those that will be committed to helping us build a better server product.

What You Will Do

• Responsible for implementation on large state-of-the-art server-SoC blocks, including synthesis, timing constraint generation, timing closure, equivalency checking, function ECO, placement, CTS, route and other sign-off
• Run physical synthesis on large and medium size blocks
• Implement and verify other aspects netlist generation like scan-insertion, clock-gating checks, power-domain checks, etc...
• Develop mid-end to back-end implementation flows on synthesis, placement, CTS, Route, timing analysis, eco-generation, etc..
• Define timing constraints at block and top level across all modes (Functional /BIST /SCAN /JTAG) and corners
• Perform timing closure across all corners to ensure successful tape-out following our aggressive deadlines
• Generate and implement functional ECO
• Run Logic Equivalent Check (LEC) from RTL to pre-layout/ post-layout netlist
  
  

What You Will Bring

• Minimum 5+ years of development mid-end to back-end implementation flows
• Experience with Verilog or HDL languages and tools is a plus
• Experience in scripting languages (PERL, TCL, shell, etc.)
• Experience in ASIC methodologies and tools like Genus, Cadence Innovus, Synopsys Primetime, Cadence Tempus, LEC, CDC, etc.
• Physical design experience a plus
• Synthesis, place and route and Timing analysis experience
• Good English and Vietnamese communications skills, both speaking and writing
  
  

Education

• BS/MS/Ph.D. in Electronic Engineering/Computer Engineering or equivalent
  
  

Our Company

Ampere is designing the future of hyperscale cloud and edge computing with the world’s first cloud native processor. Built for the cloud with a modern 64-bit Arm server-based architecture, Ampere gives customers the freedom to accelerate the delivery of all cloud computing applications. With industry-leading cloud performance, power efficiency and scalability, Ampere processors are tailored for the continued growth of cloud and edge computing.

Our Story

Like the scientist behind its name, Ampere employees are innovators. We understand the needs of cloud computing and different software requirements. We are inventing what comes next and looking at everything from the structure of memory and how efficient the system is, to considerations on speed, cost of electricity and ability to cool. Power, size, weight and cost are driving the technology requirements and the innovation to come.

Our world class team of engineers, with depth and expertise in the cloud and semiconductor industries, is not only focused on the development of new semiconductor designs but also building out the first software ecosystem for Arm®-based server processors. Through the Ampere approach to the cloud and edge, we give our customers the freedom to challenge the status quo and accelerate next-generation data centers for the most memory-intensive applications. Given the challenge we have outlined, we are building a culture of entrepreneurs that ensure customers come first, proactively approaching industry challenges in the areas of security, power and performance, delivering results that matter most.

Ampere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.