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Job Description

• Develops the logic design, register transfer level (RTL) coding, simulation.
• Participates and collaborates in the definition of architecture and microarchitecture features of the block, subsystem, and SoC.
• Develops HVM content for rapid bring up and ramp to production on the automatic test equipment (ATE).
• Optimizes logic to qualify the design to meet power, performance, area, timing, test coverage, DPM, and test time/vector memory reduction goals as well as design integrity for physical implementation.
• Reviews the verification plan and drives verification of the design to achieve desired architecture and microarchitecture specifications.
• Ensures design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.
• Integrates blocks into functional IP and SoC and supports SoC customers to ensure high quality integration of the IP block.
• Collaborates with post-silicon and manufacturing team to verify the feature on silicon, support debug requirements, and document all learnings and improvements requirement in design and validation.
• Drives high test coverage through structural and specific IP tests to achieve the quality and DPM objectives of the product and develops HVM content for rapid bring up and production on the ATE.
  
  

Qualifications

We are looking for B. Eng or M. Eng in Electronics, Computer or Electrical Engineering graduates who are recent graduates or have 1-4 years of digital design exposure and experience.

• Job Working experience in verification and integration activities including but not limited to test-plan development, test writing, debug, integration and familiar with verification methodologies such as OVM, UVM or VMM.
• Enjoy pick up protocol knowledge in I/O specifications such as USB2, USB3, SATA, PCIe.
• Genuine curiosity into microprocessors, computer system architecture and high speed design as well as producer consumer transactions.
• Also dedicated and proficient in digital state machine architecture and logic design.
• Working level mastery of Unix based design environment, industry standard digital design tools, scripting languages and ASIC flows
  
  

Inside this Business Group

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here.

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Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.