Tweet
Facebook
Copy Link
- Reciving order by specification of function and specification of mouting on circuit .
- Designing and programming according specification and confiring the verification.
- Programing by Verilog/System Verilog for RTL or by SystemC/C/C++ for high-level synthesis.
- Verifying environment construction & scenario in SystemVerilog/SVA/UVM/C.
*** Working day & time: Mon - Fri, 8:30～17:30 (Flexitime system - core time - 10:00~15:00).
*** Working place: Dist. 3 (3 months) & Tokyo, Japan.
*** Benefit:
- Bonus : 2 time per year.
- Lunch allowance.
- Commuting allowance.
- Child allowance (women)
- Long-term service allowance (5 years or more)
- Travel allowance (domestic/overseas)
- Company trip.
- Language/technical acquisition allowance.
- Individual insurance support.
- Company uniform.