Golden Gate

We Are:

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are a seasoned SOC Engineering professional with a passion for innovation and problem-solving. With a strong background in Electronics Engineering, Electromechanics, or Telecommunications, you bring hands-on experience in Place & Route domains using advanced tools like Fusion Compiler/ICC2. You have a keen understanding of P&R, extraction, timing, IREM, and Physical Verification fundamentals. Your proficiency in scripting languages such as TCL and PERL, combined with your ability to guide and mentor junior team members, sets you apart. You thrive in collaborative environments, working closely with cross-functional teams including Business Units and Sales, to develop and deploy cutting-edge tool and IP solutions. Your excellent communication skills enable you to articulate complex technical concepts effectively in English.

What You’ll Be Doing:

• Developing and implementing SOC design using Synopsys EDA tools and IP, covering all stages from spec to post-silicon bring-up.
• Contributing to both turnkey projects and serving as a trusted advisor to customer design and CAD teams.
• Innovating solutions to problems independently, with occasional guidance.
• Setting task-level goals and consistently meeting schedules.
• Collaborating with other Synopsys teams, including BU AE and Sales, to broaden and deploy tool and IP solutions.
• Providing technical guidance and mentorship to junior team members.
  
  

The Impact You Will Have:

• Enhancing the efficiency and effectiveness of SOC design processes.
• Driving innovation in chip design and verification methodologies.
• Ensuring the successful deployment of Synopsys' EDA tools and IP solutions.
• Improving customer satisfaction through expert advisory and technical support.
• Contributing to the development of high-performance silicon chips and software content.
• Supporting the continuous technological advancements at Synopsys.
  
  

What You’ll Need:

• BS/MS/PhD in Electronics Engineering, Electromechanics, or Telecommunications.
• 5 to 12 years of hands-on experience in Place & Route domains using Fusion Compiler/ICC2 tool.
• Strong debugging skills and a good understanding of P&R, extraction, timing, IREM, and Physical Verification fundamentals.
• Experience with signoff tools like PT, Redhawk, StarRC, ICV is an advantage.
• Proficiency in TCL/PERL scripting.
  
  

Who You Are:

• Innovative problem solver with the ability to work independently and as part of a team.
• Effective communicator with strong English language skills.
• Mentor and leader capable of guiding junior team members.
• Collaborative team player who can work with cross-functional teams.
• Detail-oriented professional with a focus on meeting schedules and goals.
  
  

The Team You’ll Be A Part Of:

You will be an integral part of our SOC Engineering team, which focuses on developing and implementing advanced SOC designs using Synopsys EDA tools and IP. The team collaborates closely with other Synopsys teams, including Business Units and Sales, to deliver innovative solutions that drive the future of technology.